Recent work on developing a chip architecture, suggests existing FPGAs are more suitable than earlier thought, as targets for synchronic computation. Strategically and practically this would offer considerable benefits. Consequently a pivot away from chip design, to focus exclusively on novel forms of high level synthesis is being considered.
The Synchronic Approach
Isynchronise is developing innovative approaches to languages, compilers and reconfigurable processors, arising from a novel textual language system, and associated families of formal models of computation. The basic insight is that textual programming languages have until now been based on a natural language based conception of the relationship between syntax and semantics, which historically evolved…
Public forum discussion on SC
There is some good discussion on the spatial approach and synchronic computation here; (http://lambda-the-ultimate.org/node/5614).
Interpretable Machine Learning
Interpretable machine learning is potentially landmark research. Developed originally at Duke University and then at the University of Maine, ProtoPNet provides a means of resolving the mystery of how deep neural networks classify inputs.
What future for the Von Neumann paradigm?
What future for the Von Neumann paradigm of computer architecture? AMD is to acquire Xilinx, after Intel got Altera. Is this the beginning of a shift away from ISA, or a last ditch attempt to rescue it?
Will micro-fluidics solve thermal issues with 3D-ICs ?
The promise of monolithic 3d integrated circuits, with multiple die layers connected through monolithic vias, has been held back in part by their thermal characteristics. This research from Ecole Polytechnique Federale de Lausanne may offer a solution by combining microfluidics and electronics within the same die layer to produce a monolithically integrated cooling structure. #3dChips…
Retuning transistors to replace LUTs?
Currently logic functions in reconfigurable architectures are implemented using relatively large scale LUTs. This research from Nanjing University and the National Institute for Materials Science in Japan, shows how just several transistors making up the same logic circuit, can be tuned to implement a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. #fpgas #circuits…
There will be a conference talk at BCTCS 2020, if it is still going ahead, on alpha-rams in April : The alpha-ram family – bit level models for parallelism and concurrency. Abstract There are no bit-level machine models for parallelism and concurrency, amongst the standard formal models of computation, that permit computer…
deterministic implementation of concurrency
Deterministic treatments of concurrency are largely confined to synchronous programming for reactive systems, sometimes web based but often involving embedded devices, controlled by real time operating systems. For more general purpose computing in what are considered to be asynchronous environments, nondeterministic concurrency, expressed by process algebras and their derived languages, is often chosen. Is there an alternative to non-determinism in the general case?
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