Isynchronise Enters Global IP Expansion Phase Isynchronise has moved into a high-intensity Intellectual Property (IP) development cycle. As the preparation to scale the programmable DSP and system control solutions globally, securing the innovations is a top priority. Strategic Focus: Patent protection will be filed across key jurisdictions, with a specific focus on the Far…

Isynchronise has been an open source project to identify the legacy issues inherited from natural language impacting parallelism and high performance computing, and to refactor formal and programming language structures, and downstream models of computation. To advance the project generally, and to develop new architectural concepts for a system control chip and a programmable DSP…

New work involves a programmable DSP aimed at advanced predictive modelling, image enhancement, computer vision, and adaptive filtering. Although the Synchronic approach offers significant benefits, wire based connectivity poses a chip area challenge, which does not however apply in the context of a programmable DSP.

Recent work on developing a chip architecture, suggests existing FPGAs are more suitable than earlier thought, as targets for synchronic computation. Strategically and practically this would offer considerable benefits. Consequently a pivot away from chip design, to focus exclusively on novel forms of high level synthesis is being considered.

Isynchronise is developing innovative approaches to languages, compilers and reconfigurable processors, arising from a novel textual language system, and associated families of formal models of computation. The basic insight is that textual programming languages have until now been based on a natural language based conception of the relationship between syntax and semantics, which historically evolved…